Bringing up lower level metal nodes of multi-layered IC devices is necessary for IC device modification or re-routing, as well as being useful for debugging and failure analysis. The task of bringing up these lower level metal nodes is often difficult and tedious, especially when desired or target metal nodes or layers are buried under other higher level or non-target metal nodes or layers. As a result, not only are target nodes difficult to access, but also, undesired shorts are difficult to prevent. To further complicate the situation, as the number of metal layers increases, the lower level metal nodes become increasingly thinner, and the node population becomes increasingly more dense. These conditions result in a decreased success rate reaching a desired lower level metal node.
Problems reaching desired metal nodes are exacerbated when there is limited frontside access, such as in flip-chip, multi-layer IC devices. FIG. 1 illustrates a sideview of a portion of a typical flip-chip configuration. As shown in FIG. 1, an IC device 10 is coupled to a ceramic package 12 (e.g., a C4 package) via solder bump 14. The solder bump 14 acts as a chip-to-carrier interconnect to attach the IC device 10 to the ceramic package 12 and to mate with corresponding pad patterns to form the necessary electrical contacts between the circuit(s) of the IC device 10 and pins of the package 12. To reach the desired nodes of the IC device 10, the thick silicon substrate 16, e.g., on the order of 530 microns (.mu.m) thick, which is the top layer seen from the backside of the IC device 10, must be removed.
A common approach to reduce the silicon thickness is to utilize mechanical polishing of the device. The mechanical polishing used from the backside removes the silicon and creates a very thin device. The reduced thickness allows utilization of an infrared (IR) optical device to view the device, while performing some diagnostic analysis on device functionality. Unfortunately, the thin device created by polishing is difficult to handle and subsequently utilize in further device analysis, which normally requires the removal of the device from the package to perform more testing and inspection from the frontside of the device. Breakage of the device often occurs due to the thinness of the device and brittleness of the silicon. Thus, the process is highly problematic and significantly time-consuming.
Alternatively, RIE (reactive ion etching) is generally used as a global delayering method. In RIE, a frontside plasma etch normally removes passivation layers and dielectric layers to expose the metal layers of all the transistors in a given device. But, difficulties exist in utilizing RIE from the backside. While the techniques of RIE are established for frontside etching with stop points well-defined and understood, backside etching is less established. Thus, RIE is not considered an optimal technique for accessing nodes from the backside, especially since attempts to achieve a non-uniform etching in which only desired portions of a device are exposed may result in over-etch problems.
Another possibility is the utilization of a FIB (focused ion beam) system. With FIB utilization from the frontside, individual areas are exposed through the use of a focused ion beam. FIB techniques normally use a low level current, i.e., less than about 1000 picoamperes (pA), to open individual areas, e.g., windows of approximately 15 micron (.mu.m).times.15 .mu.m. Unfortunately, such low levels of current result in significantly long time periods to open the windows, for example, on the order of thirty minutes per window. Further, when the FIB is used for desired nodes in lower levels, if the FIB window is not opened wide enough, the depth of the trench formed by etching through the upper layers limits the detection of a signal coming back from the node during e-beam (electron beam) probing. Normally, the desired aspect ratio (ratio of height to width) of the trench is 1:1, which is difficult to achieve in the lower level nodes due to the narrow width and increased depth of the trenches. These problems are even more significant from the backside, since the use of the FIB to etch through the thick silicon layer on the backside is considered highly time-consuming and thus is usually avoided. While a specially designed FIB exists for quick removal of bulk silicon material, such a FIB is expensive and limited to use on the backside. Thus, it does not provide a practical solution for most environments.
Accordingly, a need exists for exposing desired nodes at local areas from the backside efficiently and accurately for IC devices utilized in package orientations that limit frontside access. The present invention addresses such a need.